2010
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SATA MOI – PHY-TSG-OOB: Serial
ATA Interoperability Program Rev. 1.3, Ver. 1.0 SyntheSys Research, Inc.
MOI for PHY, TSG & OOB Tests (using BERTScope 7500B with CR) •
Revision 1.3 • Version 1.0 • JUNE 2010
Description +
- These Methods of Implementations describe the
step-by-step procedures to perform the required PHY-01 through
PHY-04, TSG-01 through TSG-12 (except TSG-07 and TSG-08, which
are obsolete), OOB-01 through OOB-07 tests of the Serial ATA
Interoperability Program, using the BERTScope by SyntheSys
Research, Inc., in order to qualify a product for listing on
the SATA Integrators List. This MOI is a lot simpler and a
lot shorter than the previous versions, although it includes
seven additional OOB tests. This is due to the leverage of
the new PatternVu software option which improves accuracy of
amplitude, rise time and skew measurements and the inclusion
of functions integrated in the latest BERTScope software.
The test setup is illustrated in Appendix E, including a
simplified version of this setup for OOB tests. The tests
may be performed in sequence using automated software shown
in "Test Title: Serial ATA Interop Test Suite." Please
contact SyntheSys Research, Inc. at +1 (650) 364-1853 or info@bertscope.com for the availability
of software and accessories.
Download PDF - 3.1 MB |
 |
SATA MOI – PHY-TSG-OOB: Serial
ATA Interoperability Program Rev. 1.3, Ver. 1.0RC SyntheSys Research, Inc.
MOI for PHY, TSG & OOB Tests (using BERTScope 7500B with CR) •
Revision 1.3 • Version 1.0RC • APRIL 2010
Description +
- These Methods of Implementations describe the
step-by-step procedures to perform the required PHY-01 through
PHY-04, TSG-01 through TSG-12 (except TSG-07 and TSG-08, which
are obsolete), OOB-01 through OOB-07 tests of the Serial ATA
Interoperability Program, using the BERTScope by SyntheSys
Research, Inc., in order to qualify a product for listing on
the SATA Integrators List. This MOI is a lot simpler and a
lot shorter than the previous versions, although it includes
seven additional OOB tests. This is due to the leverage of
the new PatternVu software option which improves accuracy of
amplitude, rise time and skew measurements and the inclusion
of functions integrated in the latest BERTScope software.
The test setup is illustrated in Appendix E, including a
simplified version of this setup for OOB tests. The tests
may be performed in sequence using automated software shown
in "Test Title: Serial ATA Interop Test Suite." Please
contact SyntheSys Research, Inc. at +1 (650) 364-1853 or info@bertscope.com for the availability of software and accessories.
Download PDF - 2.6 MB |
|
Stress Calibration for Jitter >1UI — A Practical
Method • MAR 2010
Abstract +
- While measuring the amount of jitter present on a signal
is relatively straight forward conceptually when the levels of jitter are
small, amounts above a bit period (1 unit interval or UI) can be more
difficult. This has practical consequences for standards such as USB 3.0
where calibration at the test device of 2 UI at 500 kHz of sinusoidal
jitter is required. This note describes use of patterns and triggering
on a BERTScope to allow such calibration.
(SR-TN092)
Download PDF - 487 kB |
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Webcast: New Test
Requirements for 40/100 GbE Transceivers •
Presenters: Charlie Schaffer, SyntheSys
and Pavel Zivny, Tektronix •
Sponsored by SyntheSys, in association with Tektronix •
On-Demand Webcast hosted by Lightwave • MAR 2010
Abstract +
- Strong user demand is ahead of the development
of the latest high speed Ethernet standards. Learn about some
of the newest physical layer test requirements for the new
40/100 GbE standard as we give an overview of measurements and
solutions in this rapidly evolving field.
Register to Watch Webcast from
Lightwave |
|
Webcast: USB 3.0 Receiver
Compliance Testing • Presenter: Cynthia Nakatani •
Sponsored by SyntheSys • On-Demand Webcast
hosted by Test & Measurement World • FEB 2010
Abstract +
- Early development efforts for 16x Fibre channel
are proceeding ahead of the completion of the new standard. In
anticipation of the new market need, many transceiver and component
vendors are evaluating new and existing designs at the 14.025 Gb/s
data rate. We will outline the key performance requirements and
corresponding measurement methods for transmitter and receiver
evaluation.
(See related white paper below)
Register to Watch Webcast from
T&MW |
|
USB 3.0 Receiver Compliance Testing • JAN 2010
Abstract +
- SuperSpeed USB (USB 3.0) promises to become
as popular and widespread as its predecessors. At 5 Gb/s,
however, it is more than an order of magnitude faster than
USB 2.0, posing challenges for physical layer testing. This
paper reviews the requirements for receiver compliance
testing with an example using the BERTScope family of
products.(SR-TN091)
See related webcast, above
Download PDF - 3.6 MB |
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Characterizing an SFP+
Transceiver at the 16G Fibre Channel Rate • JAN 2010
Abstract +
- Learn more about compliance testing to the
16G Fibre Channel standard. This paper demonstrates how an SFP+
Transceiver can be characterized at the 16G Fibre Channel rate
of 14.025 Gb/s with the help of the BERTScope Si 17500C and
BERTScope CR 14300A.
(SR-TN090)
See related Webcast
below
Download PDF - 3.4 MB |
2009
|
'Six Sigma' Mask Testing • NOV 2009
Abstract +
- This short note describes some strengths and
weaknesses of ‘Six Sigma,’ or ‘6σ’
mask testing, a methodology that gives increased measurement depth
compared to traditional shallow mask testing. It uses tutorial
material taken from an earlier paper* to provide some context,
as well as measured results. (SR-TN089)
*Optical Transmitter Jitter Measurement
Basics
Download PDF - 0.6 MB |
|
Webcast: Characterizing an
SFP+ Transceiver at the 16x Fibre Channel Rate •
Presenter: Charlie Schaffer •
Sponsored by SyntheSys in association with Tektronix • On-Demand Webcast
hosted by Lightwave • OCT 2009
Abstract +
- Early development efforts for 16x Fibre channel are
proceeding ahead of the completion of the new standard. In anticipation
of the new market need, many transceiver and component vendors are
evaluating new and existing designs at the 14.025 Gb/s data rate. We will
outline the key performance requirements and corresponding measurement
methods for transmitter and receiver evaluation.
(See related white paper
above)
Register and Watch Webcast
from Lightwave |
|
BERTScope Jitter Map Comparison Study
• SEPT 2009
Abstract +
- As any signal integrity engineer can
tell you, there is more than one way to measure jitter.
Engineers are faced with a plethora of test instruments,
including sampling oscilloscopes, real-time oscilloscopes,
and bit error ratio testers (BERTs), all using their
own methods to acquire data and measure jitter. The
reality is that sometimes jitter answers from different
instruments will be the same, and sometimes they will
differ, depending on the conditions of the signal under test.
This paper is not a comparison of methodologies between
different instrument types. Rather, its goal is to provide
empirical data that demonstrates how the BERTScope Jitter
Map jitter decomposition performs compared to the Agilent
86100C Infiniium DCA-J Jitter Mode product over a range of
signal conditions. (SR-TN086)
Download PDF - 2.9 MB |
|
Measurement Brief: D.C. Blocks, a Trap for the
Unwary when Using Long Patterns • JULY 2009
Abstract +
- It is common in high speed digital applications
to use a d.c. block in test setups. For example, it can be useful to
isolate a component – such as an optical receiver that requires a
bias voltage on the signal path – from either damaging or being
damaged by other instruments in the signal path. In addition to
attributes such as low insertion loss and good return loss, a key
specification of a d.c. block is its frequency response. It is
obvious to focus on ensuring that the upper frequency of the range
is adequate to pass the desired data signal; while it is less obvious
to worry about the low end frequency specification, we will see that
it can be equally important.
(SR-TN088)
Download PDF - 0.2 MB |
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克服闭合的眼 – 设计和测量应对信道损耗的预加重和均衡
• Combating Closed Eyes — Design and Measurement of Pre-Emphasis
and Equalization for Lossy Channels •
On-Demand Webcast • JUNE 2009
简介 +
-
本次研讨会将会介绍为通过损耗的信道传输的高速串行数据，例如：计算机底板,
线缆以及连接器等预加重和均衡的
必要性。为了克服由频率相关信道损耗导致的码间干扰现象，
可以在不同的信号处理节点进行反向传递函数的计算
和应用，从而进行无误码检测。
执行反向传递函数的电路，例如预加重和均衡，
包括数字有限脉冲响应(FIR)滤波器，线性有限脉冲响应(FIR) 均衡器
以及判决反馈均衡器 (DFE)。在理论上的滤波器进行说明以后，
将会举例说明由阶跃响应或频域网络分析测量方法而
产生优化脉冲响应滤波器。会提到相关测量方法，PCI Express的例子也会被作为标准引用。
(See this webcast
in English)
(See related white paper
in English, below)
迎参加在线研讨会，注册用户请先登
(See this webcast in English) |
|
Case Study: Using BERTScope Jitter Map to Troubleshoot
a Curious ISI Issue • MAY 2009
Abstract +
- An interesting signal integrity problem in
a Gb/s circuit was successfully identified with BERTScope Jitter Map.
Here we look at the issue, its cause, and explain what was going on.
(SR-TN087)
Download PDF - 0.7 MB |
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Product Note: Getting the Right Stress at the IC Pins —
De-Embedding with BERTScope • APR 2009
Abstract +
- A methodology for delivering an accurate, calibrated
compensation of a 17-inch trace to deliver a compliant SFP+ stressed eye
as an example. (SR-TN084)
Download PDF - 0.6 MB |
|
BERTScope Jitter Map "Under the Hood" —
A New Methodology for Jitter Separation • APR 2009
Abstract +
- Jitter Map is a new capability on the BERTScope that
uses BER measurements to measure Total Jitter as well as decompose jitter
beyond basic Random and Deterministic Jitter. This paper introduces the
reader to the methodologies used in this innovative tool, and explains
novel features which allow users to delve into jitter problems in new
ways, such as examining Random Jitter on each edge of the data pattern,
separating out the jitter caused by transmitter pre-emphasis, and
performing jitter decomposition on long patterns such as PRBS-31.
(SR-TN085)
Download PDF - 1.3 MB |
|
Why Do Different Instruments Give Different
Jitter Answers? • MAR 2009
Abstract +
- A common complaint amongst signal integrity engineers is
that every high speed instrument in their laboratory gives them a different
answer when they measure jitter. This paper looks at some generic instrument
types (‘real time’ scope or ‘DSO,’ ‘equivalent-time’ or sampling scope, and
BERT or BERTScope) and examines why answers can be different. The intent is
not to identify one type as universally correct — unfortunately such an
instrument does not exist for all situations. It does, however, aim to give
guidance on certain conditions where some methods do better than others.
This paper is based on an eSeminar given with EDN Magazine, February 2009.
(SR-TN083)
See related Webcast link below
Download PDF - 1.8 MB |
|
Webcast: Why Different Instruments Give You Different
Jitter Answers • Presenter: Charlie Schaffer •
On-Demand Webcast • FEB 2009
Abstract +
- The fact that lab instruments, whether of different
types, or models within the same type, give frustratingly different
measured results for the same target device is not news to most
engineers. Here we explore some underlying reasons why this occurs.
(See related white paper above)
Register and Watch Webcast |
|
Product Note: Testing an SFP+ Transceiver to the 10 Gigabit
Ethernet Electrical Specifications • FEB 2009
Abstract +
- This paper examines the transmitter electrical input
specifications and receiver electrical output specifications of a limiting
variant SFP+ transceiver and active SFP+ cable for 10 Gigabit Ethernet
(10GbE) applications. It covers electrical testing requirements for
transmitter and receiver test points B’ and C’ of the SFP+ module, and
provides a practical example that demonstrates compliance testing of
the SFP+ electrical specifications for 10GbE applications. (SR-TN082)
Download PDF - 1.6 MB |
|
SATA MOI – RSG: Serial ATA Interoperability Program
Revision 1.3 SyntheSys Research, Inc. MOI for RSG Tests (using BERTScope
7500B with CR) • Revision 1.3, Version 1.0 • FEB 2009
Description +
- These Methods of Implementation describe the
step-by-step procedures to perform the RSG-01 through RSG-02 tests
of the Serial ATA Interoperability Program using the BERTScope by
SyntheSys Research, Inc. to qualify a product, host or device, for
listing on the SATA Integrators List. Described methods can test
products which support disconnect as well as products without
support of disconnect.
• The test setup is illustrated in Appendix B.
• The Framed COMP pattern used for Interoperability Testing is the pattern
defined in SATA_Pretest_MOI revision 1.3 which can be found at
http://www.serialata.org/testing.asp.
The tests can be performed in automated fashion using Jitter Tolerance
software available on the BERTScope. Contact SyntheSys Research, Inc.
at +1 (650) 364-1853 or info@bertscope.com
for the latest information on such software.
Download PDF - 1.7 MB |
|
Measuring PLL Loop Bandwidth Using a BERTScope
• JAN 2009
Abstract +
- Understanding phase lock loop (PLL) response is important for the design and
verification of digital communication networks. In this paper we will show PLL measurement
examples, each made using the BERTScope with automation software. First, the measurement of
a PLL response for 5 GT/s PCI Express is shown, and
second a 200 MHz PLL. (SR-TN081)
Download PDF - 1.3 MB |
|
PCI Express®
5.0 GT/s Add-In Card Receiver (Base Specification) Testing, Rev. 1.2 •
JAN 2009
Abstract +
- The need to relieve throughput bottlenecks in computing and communications,
together with the development of low cost, high speed CMOS technology, has caused the move to
high speed serial buses. PCI Express (PCIe) is aimed at replacing PCI for applications such
as interfacing video cards in computing. Because the PCIe serial data rates of 2.5 GT/s and
5.0 GT/s are in the microwave range, they require significant attention to signal integrity
for successful compliance testing. Testing can be done at two levels: the Base Specification; or
the Card Electro-Mechanical (CEM) level, a subset of the full base specification used for
compliance workshops. This document describes testing to verify receiver compliance with the
PCI Express Base Specifications Revision 2.0 and highlights three important areas in receiver
compliance testing:
• Jitter generator requirements including clock recovery
• Calibration channel requirements
• Compliance baseboard configuration requirements
(SR-TN071)
Download PDF - 2.1 MB |
2008
|
PCI Express®
5.0 GT/s Add-In Card Receiver CEM Testing • DEC 2008
Abstract +
- The need to relieve throughput bottlenecks in computing and
communications has caused the move to high speed serial buses. While 5.0 GT/s PCI
Express (PCIe) is aimed at improving throughput for graphics or memory intensive
applications such as interfacing video cards in computing, 5 GT/s is also favored
over 2.5 GT/s as fewer lanes, but at higher speed, often reduce the cost of the
Add-In card. Because the PCIe serial data rates of 2.5 GT/s and 5.0 GT/s are in
the microwave range, they require significant attention to signal integrity for
successful compliance testing. Testing can be done at two levels: the Base
Specification, or the Card Electro-Mechanical (CEM) level, a subset of the full
base specification used for compliance workshops. This document describes testing
to verify receiver compliance with the PCI Express Card Electro-Mechanical (CEM)
Specification Revision 2.0 and highlights four important areas in receiver
compliance testing:
• Jitter generator requirements including jitter spectrum
• Use of 4-tap de-emphasis to obtain specified voltages at compliance point
• How rise time filters makes the test signal follow the mask optimally
• Compliance Base Board configuration requirements which still allow toggling
for transmitter compliance tests
(SR-TN080)
Download PDF - 3.1 MB |
|
10GBASE-KR Compliance Testing, Rev. 1.1 • DEC 2008
Abstract +
- A few years ago, microwave signals were often transported through
waveguide, coax cables, and microwave microcircuits. Serial data communi¬cations now
regularly occurs at 10 Gb/s across low cost circuit board materials, with 10 Gigabit
Ethernet over Backplane being an example. This paper takes a look at selected
requirements of IEEE Standard 802.3ap™-2007 (also known
as 10GBASE-KR), what the measurements mean, and a practical example. (SR-TN079)
Download PDF - 1.9 MB |
|
SATA MOI –
PHY-TSG: Serial ATA Interoperability Program Revision 1.1
SyntheSys Research, Inc. MOI for PHY and TSG Electrical Tests using
the BERTScope • Revision 1.1, Version 1.0 • JULY 2007 •
Final NOV 2008
Description +
- These Methods of Implementation describe the
step-by-step procedures to perform the required PHY-01 through
PHY-04 and TSG-01 through TSG-12 (except TSG-07 and TSG-08, which
are optional for all components) tests of the Serial ATA
Interoperability Program using the BERTScope by SyntheSys
Research, Inc. in order to qualify a product for listing on
the SATA Integrators List.
• The test setup is illustrated in Appendix B.
• The Lone Bit Pattern (LBP) used for Interoperability
Testing is that which is defined per ECN 018 against SATA Revision 2.5.
The tests may be performed in the sequence shown in Appendix D or
automated using software shown in "Test Title: Serial ATA Interop
Test Suite." Contact SyntheSys Research, Inc. at +1 (650) 364-1853 or
info@bertscope.com
for the availability of software and accessories.
Download PDF - 1.7 MB |
|
Comparing DCD and F/2 Jitter • SEPT 2008
Abstract +
- Duty Cycle Distortion (DCD) has been a term used to
describe conditions where the duration of an individual bits may vary.
A new variant of DCD is becoming common, called F/2, or simply F2. This
note explains how F/2 differs from classic DCD.
Download PDF - 126 kB |
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Webcast: Demystifying Receiver Jitter Tolerance
Testing •
Presenter: Steve Sekel • On-Demand Webcast originally hosted by EDN •
SEPT 2008
Abstract +
- Although all serial data standards specify a required receiver
jitter tolerance, compliance testing of the link physical layer has generally
ignored the receiver. However as the data rates are increasing, the standards
organizations are realizing that testing only the transmitter and relying on
interoperability test to cover the receiver will not assure data integrity.
Thus, the newer standards are beginning to incorporate receiver jitter
tolerance testing as part of the “gold suite” of required
compliance tests. During this test, a known compliance pattern is sent to
the receiver, superimposed with a calibrated amount of jitter. Many designers
who have only dealt with transmitter testing have questions of what is involved
with a receiver test, and how to set it up correctly.
This seminar fills the knowledge gaps by:
• Explaining receiver testing
• Giving insight into the sometimes complicated “recipe”
of jitter sources used in the test, including random, periodic, duty cycle
distortion, and inter-symbol interference.
• Showing how these jitter sources relate to the interference mechanisms
in the real communication channel.
• Explaining how to properly calibrate the jitter sources to assure
accurate testing to the standards, without overstressing the receiver.
We will also discuss special requirements for testing receivers using spread
spectrum clocking, or when transmitter pre-emphasis equalization is used.
Register and Watch Webcast |
|
Testing an SFP+ Transceiver to the 8x Fibre Channel Specifications,
Part II • AUG 2008
Abstract +
- This paper examines the practical aspects of testing
a limiting variant SFP+ transceiver for 8x Fibre Channel (8xFC or 8GFC)
applications. It covers testing requirements for transmitter and receiver
test points of an SFP+ module, including the 8GFC SFP+ high speed serial
electrical interface (SFI) interface. It describes the significant tests
required for compliance testing and details testing methods to assure
the module meets the rigorous 8GFC standards established.
Part I covers the basics of compliance testing to the Fibre Channel
standard and gives an overview of the pertinent measurements and how
they can be accomplished using BERTScope instrumentation. Part II leverages
the foundation laid in Part I and continues with a practical example
that demonstrates all aspects of compliance testing highlighted in
Part I. (SR-TN077)
Download PDF - 2.7 MB |
|
Testing an SFP+ Transceiver to the 8x Fibre Channel Specifications,
Part I • AUG 2008
Abstract +
- This paper examines the practical aspects of testing a
limiting variant SFP+ transceiver for 8x Fibre Channel (8xFC or 8GFC)
applications. It covers testing requirements for transmitter and receiver
test points of an SFP+ module, including the 8GFC SFP+ high speed serial
electrical interface (SFI) interface. It describes the significant tests
required for compliance testing and details testing methods to assure the
module meets the rigorous 8GFC standards established.
Part I covers the basics of compliance testing to the Fibre Channel standard
and gives an overview of the pertinent measurements and how they can be
accomplished using BERTScope instrumentation. Part II leverages the foundation
laid in Part I and continues with a practical example that demonstrates all
aspects of compliance testing highlighted in Part I. (SR-TN076)
Download PDF - 2.6 MB |
|
Product Note: DCRJ and OmniBER OTN 10 Gb/s
Telecom Jitter Generation Correlation Study • MAY 2008
Abstract +
- The telecom Jitter Generation measurement is an
indication of how much jitter is output at an optical interface
(for example, an optical transmitter)
and is a requirement in telecom testing to standards such as
SONET/SDH and OTN. Historically, jitter analyzers have been used to
perform this measurement. A new type of instrument, the BERTScope
Digital Communications Receiver (DCRJ) 11000A,
is also capable of this measurement. In this paper, we compare the
results of the DCRJ to a jitter analyzer widely
used in the industry to demonstrate good correlation as well as the
ability of the DCRJ
to measure new data rates emerging in industry standards. (SR-TN075)
Download PDF - 2.8 MB |
|
PCIe MOI: PCI Express (Rev. 2.0) Test Methodology for PLL
Loop Bandwidth Response in Add-In Cards Testing Guide for SyntheSys
Research, Inc.'s PLL Analyzer Series BERTScope PLA, CRJ
125A-PCIE, and PLL-PCIE • Revision 1.0 • APRIL 2008
Description +
- The PLL Loop Response test measures the bandwidth
and peaking of the PLL used in Add-in cards for generating the Tx
clock from the distributed 100 MHz REF_CLK signal. The loop
response is determined by substituting a test clock, which
contains a calibrated level of sinusoidal jitter, for the locally
generated REF_CLK. The PLL analyzer measures the transferred
jitter by applying the transmitted compliance pattern output from
the Add-in card under test to a reference PLL. The phase deviation
is digitized and analyzed within the instrument to determine its
spectral components. The frequency of the modulating sinusoidal
jitter is incrementally swept, with measurement data taken at
each frequency step. The instrument computes the PLL magnitude
and phase, along with jitter transfer function, automatically.
Download PDF - 976 kB |
|
PCIe MOI: PCI Express (Rev. 1.1) Test Methodology
for PLL Loop Bandwidth Response in Add-In Cards Testing Guide for
SyntheSys Research, Inc.'s PLL Analyzer Series BERTScope PLA,
CRJ 125A-PCIE, and PLL-PCIE •
Revision 1.0 • APRIL 2008
Description +
- The PLL Loop Response test measures the
bandwidth and peaking of the PLL used in Add-in cards for
generating the Tx clock from the distributed 100 MHz
REF_CLK signal. The loop response is determined by substituting
a test clock, which contains a calibrated level of sinusoidal
jitter, for the locally generated REF_CLK. The PLL analyzer
measures the transferred jitter by applying the transmitted
compliance pattern output from the Add-in card under test
into a reference PLL. The phase deviation is digitized and
analyzed within the instrument to determine its spectral
components. The frequency of the modulating sinusoidal jitter
is incrementally swept, with measurement data taken at each
frequency step. The instrument computes the PLL magnitude
and phase, along with jitter transfer function, automatically.
Download PDF - 855 kB |
|
|
Optical
Transmitter Jitter Measurement Basics • APR 2008
Abstract +
- While jitter is a familiar measurement in optical transmitter
testing, it can be defined very differently depending on the context. We will
compare and contrast the meanings for telecom standards such as SONET/SDH/OTN
with those for enterprise and storage. We will explore eye diagram jitter
compliance and the different philosophies behind bathtub jitter and the frequency
banded jitter relied on in other standards. The implications for compliance and
troubleshooting will be illustrated with measurement examples.
This paper is based upon an e-seminar given by SyntheSys Research in January 2008
through Lightwave Magazine. (SR-TN074)
See related On-Demand Webcast link below
Download PDF - 2.5 MB |
|
Comprehensive Optical Stressed Eye and Transmitter Compliance
Testing • APR 2008
Abstract +
- Combine the BERTScope S and BERTScope DCRJ with
the 1310 nm JDSU OPTX 10 Reference Generator, or with the 850 nm BERTScope
LTS to perform stressed eye receiver tolerance and compliance testing up to
11.2 Gb/s. The test set is configurable for multiple data rates and provides
both electrical and optical stressed eye testing for XFP/XFI, 2x, 4x, and 10x
Fibre Channel, and 10GbE at 850, 1310, or 1550 nm wavelengths. This solution
gives design and test engineers deep insight into device performance with
eye diagram, jitter peak, jitter spectrum, compliance contour, and BER
contour analyses.
• Accurate analysis of stress elements to provide calibrated signal at the
test device input
• Automated testing to standard or custom jitter tolerance templates with
user-defined stress margins
• Optical reference transmitter with pre-calibrated, adjustable extinction
ratio
• Test to standards requiring compliant loop bandwidth clock recovery using
the BERTScope DCRJ
• 10 Gb/s Transmitter Compliance Testing
• SONET, SDH, and OTN Jitter Generation Analysis including 11.1 Gb/s
(SR-DS017)
Download PDF - 2.7 MB |
|
Combating Closed Eyes: Pre-Emphasis and
Equalization Basics • APR 2008
Abstract +
- Pre-emphasis and equalization are signal processing
techniques that are increasingly popular solutions to signal integrity
problems caused by lossy backplane channels at high signaling rates. The
goal of this paper is to show how channel loss manifests itself and how
pre-emphasis and equalization can be used to counteract this loss. We will
also examine how pre-emphasis affects test and measurement with examples
pulled from popular standards. We conclude with some practical examples of
pre-emphasis and equalization filters across a high speed backplane. (SR-TN073)
See related Webcast link below
Download PDF - 2.2 MB |
|
DisplayPort MOI – Sink: VESA DisplayPort
PHY Sink Compliance Test Standard Version 1 SyntheSys Research,
Inc. MOI for Sink Tests (Using BERTScope 7500B) • Revision 0.26
• OCT 2007 • Released FEB 2008
Description +
- These Methods of Implementation describe the step-by-step
procedures to perform the Sink Compliance tests of the DisplayPort standard
using the BERTScope by SyntheSys Research, Inc., to qualify a product, host,
or device for listing on the DisplayPort Integrators List.
• Described methods can test products which support disconnect as well as
products without support of disconnect.
• The test setup is illustrated in Appendix B.
The tests can be performed in automated fashion using Jitter Tolerance
software available on the BERTScope. Contact SyntheSys Research
(info@bertscope.com) for the latest information on such software.
Download PDF - 2.8 MB |
|
Signalintegritätsanalyse
und Compliance Testing (Signal Integrity Analysis and Compliance
Testing) • article published in electronik
industrie • Michael Riess, Laser 2000 • FEB 2008
Abstract +
- Mit den BERTScopes ist es möglich, Bitfehlermessungen
mit Augendiagramm- und Augenkonturmessungen zu korrelieren. Sehr schnelle
Maskentests, Jitter-Peak, Q-Faktor und Jitterspektrumanalyse geben weitere
Information über die Qualität der untersuchten seriellen Datensignale.
Eine detaillierte Fehleranalyse, ausgehend von der Augendiagrammdarstellung
bis hinunter auf Bitebene, wird so möglich.
[With the BERTScope it is possible to correlate bit error measurements
with eye diagram and eye contour measurements. Very fast mask tests, jitter
peak, Q-factor, and jitter spectrum analysis give further information about
the quality of the examined serial data signals. A detailed error analysis,
on the basis of the eye diagram representation down to the bit level, becomes
possible.] This English translation of the abstract is for convenience;
the article is available in German only.
Download PDF - 0.2 MB
 Read at elektronik industrie |
|
Webcast: Transmitter Jitter Basics: Two
Worlds of Test • Presenter: Charlie Schaffer • On-Demand
Webcast originally hosted by Lightwave • JAN 2008
Abstract +
- While jitter is a familiar measurement in
transmitter testing, it can be defined very differently depending on
the context. In this webinar we compare and contrast the meanings for
telecom standards such as SONET/SDH/OTN with those for enterprise and
storage. We explore eye diagram jitter compliance and the different philosophies
behind bathtub jitter and the frequency banded jitter relied on in other
standards. The implications for compliance and troubleshooting are illustrated
with measurement examples.
(See related white paper above)
Register and Watch Webcast |
|
Product Note: Telecom Jitter
Analysis Using the BERTScope and BERTScope DCRJ • JAN 2008
Abstract +
- Fiber Optic transmission systems are continuing to
push data rates to higher levels. As rates increase,
so does the negative contribution of jitter in networks.
Understanding and controlling jitter throughout the
network is key to error free transmission. Optical transceivers
are a significant component in telecom network equipment.
For an optical transceiver, it is important to establish if:
• The device receiver can tolerate
enough incoming jitter (jitter tolerance)
• The device transmitter produces too
much jitter (jitter generation)
• Passing jittered data through the
device causes an excessive increase (gain) in jitter
on the data being re-transmitted (jitter transfer)
In this paper we look at telecom jitter standards
SONET, SDH, and OTN, and how jitter affects error
free transmission. Also, through a practical example
measuring an XFP transceiver we verify the SONET
jitter standard using the SyntheSys Research BERTScope S and BERTScope
DCRJ, capable of testing beyond 11.1 Gb/s. (SR-TN072)
Download PDF - 2.7 MB |
|
DisplayPort MOI – Source: VESA DisplayPort PHY
Source Compliance Test Standard Version 1 SyntheSys Research, Inc. MOI for
DisplayPort Source Compliance Tests using the BERTScope • Revision 0.19 •
OCT 2007 • Released JAN 2008
Description +
- These Methods of Implementation describe the step-by-step
procedures to perform the Sink Compliance tests of the DisplayPort standard
using the BERTScope by SyntheSys Research, Inc., to qualify a product, host,
or device for listing on the DisplayPort Integrators List.
• Described methods can test products which support disconnect as well
as products without support of disconnect.
• The test setup is illustrated in Appendix B.
The tests can be performed in automated fashion using Jitter Tolerance
software available on the BERTScope. Contact SyntheSys Research
(info@bertscope.com) for the latest information on such software.
Download PDF - 1.7 MB |
2007
|
PCI Express® 2.5 GT/s Add-In Card Receiver
Testing, Rev. 1.1 • DEC 2007
Abstract +
- Add-in cards designed for PCI Express require numerous tests to
assure interoperability with different systems. This document describes testing to
verify receiver compliance with the PCI Express Architecture PHY Electrical Test
Considerations, PCI Express Card Electro Mechanical Specifications, and PCI Express
Base Specifications Revision, and highlights three important areas in receiver
compliance testing:
• Jitter generator requirements
• Compliance Base Board (CBB) configuration requirements
• Clocking Requirements
(SR-TN070)
Previously titled "PCI Express 1.0a and 1.1 Add-In Card Receiver Testing"
Download PDF - 1.8 MB |
|
Webcast: Pass PCI Express® Physical
Layer Compliance Testing the First Time • Presenter: Bent Hessen-Schmidt
• Webcast originally hosted by Test & Measurement World and EDN • DEC 2007
Abstract +
- With the PCIe 2.0 specification, 5.0 GT/s
and 2.5 GT/s receiver testing are emerging as key requirements for chip
designers and add-in card vendors. In this seminar we look at why the
requirements have been set the way they have, and some of the practicalities
of making the measurements. We will then look at key transmitter measurements
such as PLL characterization, jitter measurement in the presence of de-emphasis,
de-emphasis ratio, and dual port measurements. Measured examples of real
devices will be used to illustrate the requirements.
Register and Watch Webcast |
|
Webcast: Combating Closed Eyes — Design and Measurement of Pre-Emphasis
and Equalization for Lossy Channels • Presenter: Tom Waschura •
On-Demand Webcast originally hosted by EDN • OCT 2007
Abstract +
- This seminar introduces the need
for pre-emphasis and equalization for high-speed serial communication
over lossy channels such as backplanes, cables and connectors. In order
to overcome the inter-symbol interference caused by frequency dependent
channel losses, inverse transfer functions can be computed and applied
at various points of the signal processing to enable error-free bit detection.
Circuits are described that implement inverse transfer
functions such as pre-emphasis and equalization,
and that include digitally clocked finite impulse response filters, linear
finite impulse response equalizers as well as decision feedback equalizers
(DFE). Following the theoretical filter development, examples are presented
that derive optimized impulse response filter taps from step response
or frequency domain network analysis measurements. Measurements are discussed
and examples are used from standards such as PCI Express Generation 2.
(See related white paper above)
(See this webcast in Chinese on EDNChina)
Register and Watch Webcast |
|
DisplayPort MOI – Sink: VESA DisplayPort PHY Sink
Compliance Test Standard Version 1 SyntheSys Research, Inc. MOI for Sink
Tests (Using BERTScope 7500B) • Revision 0.26 • OCT 2007
Description +
- These Methods of Implementation describe the step-by-step
procedures to perform the Sink Compliance tests of the DisplayPort standard
using the BERTScope by SyntheSys Research, Inc., to qualify a product, host,
or device for listing on the DisplayPort Integrators List.
• Described methods can test products which support disconnect as well as
products without support of disconnect.
• Test setup is illustrated in Appendix B.
Testing can be automated using Jitter Tolerance software available on the
BERTScope. Contact SyntheSys Research (info@bertscope.com) for the latest information on such software.
Download PDF - 2.8 MB |
|
DisplayPort MOI – Source: VESA DisplayPort
PHY Source Compliance Test Standard Version 1 SyntheSys Research,
Inc. MOI for DisplayPort Source Compliance Tests using the BERTScope
• Revision 0.19 • OCT 2007
Description +
- These Methods of Implementation describe the step-by-step
procedures to perform the Source Compliance tests of the DisplayPort standard
using the BERTScope by SyntheSys Research, Inc., to qualify a product, host,
or device for listing on the DisplayPort Integrators List.
• Described methods can test products which support disconnect as well as
products without support of disconnect.
• Test setup is illustrated in Appendix B.
Testing can be automated using Jitter Tolerance software available on the
BERTScope. Contact (SyntheSys Research)
for the latest information on such software.
Download PDF - 1.7 MB |
|
PCI Express® Transmitter PLL Testing
— A Comparison of Methods • SEPT 2007
Abstract +
- The electrical compliance test specification
drafted by PCI-SIG requires testing loop response of the Phase Locked Loop (PLL)
used in add-in cards to generate a local transmitter clock from a 100 MHz
reference oscillator. There are several possible methods for performing
this test. This paper provides an overview of the significant ones, including
one method based on an instrumentation-quality clock recovery instrument.
The clock recovery method is a single-instrument solution that provides
superior test accuracy, resolution, and throughput at minimal cost. The
measurement output results are displayed directly without the need for
interpretation, minimizing chances for operator error. (SR-TN067)
Download PDF - 0.2 MB |
|
PCI Express® 2.5 GT/s Add-In Card Transmitter
Testing, Rev. 1.1 • SEP 2007
Abstract +
- Add-in cards designed for PCI Express require
numerous tests to assure inter-operability with different systems. This
document describes testing to verify transmitter compliance with the
PCI Express Card Electromechanical Specifications Revision 1.0a,
Revision 1.1, and Revision 2.0, and highlights three important
areas in compliance testing:
• Accurate views for de-emphasis measurements
• Edge density requirements for clock recovery
• The speed of making mask tests
(SR-TN062)
Previously titled "PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing"
Download PDF - 1.5 MB |
|
Gigabit
Signal Integrity Creates New Challenges •
article published in the BestTest Newsletter • AUG 2007
Abstract +
- It is well documented that many parallel data transfer architectures used in computing have switched over to higher speed serial data streams at Gigabits/sec. Examples include graphics card data (PCI to PCI Express) and storage communications (Parallel ATA to Serial ATA). The telecommunications industry has dealt with these higher speeds for a lot longer, but has not been forced to meet such stringent cost constraints. By engineering down to a competitive price, serial bus standards do not enjoy use of exotic microwave materials, nor are they allowed significant performance margins to make links work. A decade or two ago, signals with these frequency components would have been carried in waveguides, but to pass them across the types of circuit board materials of an average motherboard, engineers have had to get creative. (SR-TN068)
Download PDF - 377 kB
Read article at
BestTest |
|
SATA MOI – RSG: Serial ATA Interoperability Program
Revision 1.2 SyntheSys Research, Inc. MOI for RSG Tests (using BERTScope
7500B with CR) • Revision 1.2, Version 1.0 • AUG 2007
Description +
- These Methods of Implementation describe the
step-by-step procedures to perform the RSG-01 through RSG-02
tests of the Serial ATA Interoperability Program using the
BERTScope by SyntheSys Research, Inc., to qualify a product,
host, or device for listing on the SATA Integrators List.
Described methods can test products which support disconnect as
well as products without support of disconnect.
• Test setup is illustrated in Appendix B.
• The Framed COMP pattern used for Interoperability Testing
is that which is compliant with the definitions of SATA Revision
2.6 and approved ECNs against Revision 2.6.
Testing can be automated using Jitter Tolerance software available
on the BERTScope. Contact SyntheSys Research for the latest information on such software.
Download PDF - 1.2 MB |
|
SATA MOI – PHY-TSG: Serial ATA Interoperability Program
Revision 1.1 SyntheSys Research, Inc. MOI for PHY and TSG Electrical Tests
using the BERTScope • Revision 1.1, Version 1.0 • JULY 2007
Description +
- These Methods of Implementation describe the
step-by-step procedures to perform the required PHY-01 through
PHY-04 and TSG-01 through TSG-12 (except TSG-07 and TSG-08,
which are optional for all components) tests of the Serial ATA
Interoperability Program using the BERTScope by SyntheSys
Research, Inc., in order to qualify a product for listing on
the SATA Integrators List.
• Test setup is illustrated in Appendix B.
• The Lone Bit Pattern (LBP) used for Interoperability
Testing is that which is defined per ECN 018 against SATA
Revision 2.5.
Testing may be performed in the sequence shown in Appendix D
or automated using software shown in "Test Title: Serial ATA
Interop Test Suite." Contact SyntheSys Research for the availability of software and accessories.
Download PDF - 1.7 MB |
|
Integration Technologies for Pluggable
Backplane Optical Interconnect System • Alexei L.
Glebov, Michael G. Lee, Kishio Yokouchi •
Fujitsu Laboratories of America (First published by
SPIE in 'Optical
Engineering,' Vol. 46, Iss. 1, 015403) • JAN 2007
Abstract +
- Integration technologies for board-to-board
optical interconnect systems are presented. In the module
architecture, optical transmitters and receivers are placed
on the line cards and the signals are routed to the
optically passive backplane through optical jumpers. The
back-plane contains a light guiding layer with embedded
polymer waveguides (WGs) and 45-deg reflector micromirrors.
The WGs are fabricated by direct lithographic patterning
and have propagation losses as low as 0.05 dB/cm. The wedge
dicing technology is developed for fabrication of the 45-deg
micromirrors with 0.5-dB excess losses. The pluggable optical
connectors with microlens adaptors couple the light from the
optical jumpers into the backplane WGs. Evaluation of the
connector alignment tolerances demonstrates a very weak
dependence of the coupling efficiency on the axial
displacement and a more significant effect of the radial
shifts. The presented results show that the displacement
tolerances can be substantially improved with auxiliary
lenses formed on the substrate. Prototype optical
interconnect modules with integrated channel WGs, mirrors,
and assembled connectors are fabricated with insertion
losses of 5 to 6 dB. The modules successfully pass the
high-speed transmission tests at data rates up to 11 Gbit/s.
Download PDF - 1.6 MB |
2006
|
Clock recovery's impact on test and measurement
• published in LIGHTWAVE • NOV 2006
Abstract +
- Clock recovery plays a significant role
in making accurate test measurements, whether incorporated into the test setup
or as part of the device under test. As most gigabit communication systems are
synchronous, the data within them are timed against a common clock. Whether
traveling across inches of circuit board or traversing continents on optical
fiber, the relationship between the data and the clock they were timed against
can become disturbed. By extracting clock directly from the data, signal
regeneration at the receiver can be achieved correctly.
It is important to note that receivers typically improve the
incoming data signal before passing it on. A decision circuit in the receiver
re-times the data and squares up the pulses. This process depends on a clock
signal that is synchronous with the incoming data. Clock recovery within the
receiver achieves this goal, provided the re-timing clock moves in the same way
and at the same time. (SR-TN063)
Download PDF - 84 kB
Article reproduction (not printable) - 201 kB
Read article at LIGHTWAVE |
|
Signal Integrity Success in Computer and Storage
Applications • OCT 2006
Abstract +
- With the transition from parallel to high speed serial computer
communications, test methodology is also changing. Compliance testing continues to evolve,
with new signal conditioning schemes to be validated and renewed focus on transmitter
and receiver tolerance testing. For a design engineer, challenges tend to be two-fold -
whether a design passes compliance, and getting to root cause issues if it does not.
This brochure gives some examples of how the BERTScope family has proved useful to
our customers in both areas, starting with serial bus compliance testing.
Almost all of the examples used in this brochure are documented in more detail in
literature from SyntheSys Research. Reference numbers are given with each section,
and the source documents listed on the last page. (SR-DS020)
Download PDF - 1.6 MB |
|
SAS Receiver Jitter Tolerance Testing • SEPT 2006
Abstract +
- Serial Attached SCSI (SAS) is a serial communication protocol
for computer storage devices. It is designed as a replacement for SCSI, allowing
for much higher speed data transfers than previously available with the parallel
communication method of traditional SCSI. SAS is backwards compatible with Serial
ATA (SATA). SAS electrical receivers are required to pass a test of their jitter
tolerance using a stressed eye. The following tools are needed to make such a test:
• A jitter generator with common mode interference mode.
• An interference injection and test load (if testing a SATA device) both
compliant with the 100 +/- 15-ohm impedance (21.8 dB return loss) requirement.
• Compliance clock recovery with correct edge
density setting for verification of the stimulus.
This paper gives context to the requirements and describes the construction of a
compliant stressed eye signal. (SR-TN061)
Download PDF - 0.6 MB |
|
Measurement
Brief: Introduction to Measurement of Skew, Including Methods for SATA
and SAS Transmitter Compliance Testing • SEPT 2006
Abstract +
- In standards there is often a requirement to introduce skew into
measurements to see whether the device under test copes. In this context, skew
refers to a differential signal where the path length is different between each
side of the differential pair. It can often be an unintended consequence of board
layout routing, and also improperly matched test cables. Systems are usually
designed to be able to tolerate a certain amount. This measurement note will
look at several methods of measuring skew: a generic method, and then the methods
for Serial ATA (SATA) and Serial Attached SCSI (SAS). They can be accomplished
with a BERTScope and also applied to sampling oscilloscopes. (SR-TN053)
Download PDF - 0.4 MB |
|
Serial ATA Gen2 Jitter Tolerance Testing • AUG 2006
Abstract +
- Serial ATA is an increasingly common serial bus technology aimed at disk drive applications. Electrical receivers are required to pass a test of their jitter tolerance using a stressed eye. This paper gives context to the requirements, and describes the construction of a compliant stressed eye signal.
(SR-TN054)
Download PDF - 1.1 MB |
|
Testing the High Speed Electrical Specifications of an
XFP Transceiver • JULY 2006
Abstract +
- This paper takes a look at the practical aspects of testing an XFP transceiver. It covers testing requirements for the host system output (B´) and the XFP module output (C´). It describes the various tests required for compliance testing of an XFP transceiver and describes testing methods to assure the module meets the rigorous standards. (SR-TN060)
Download PDF - 2.0 MB |
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SATA MOI – PHY-TSG: Serial ATA Interoperability Program MOI for PHY and TSG Certification Tests using the BERTScope by SyntheSys Research, Inc. • Revision 1.0, Version 1.0 • JUNE 2006
Description +
- These Methods of Implementation describe the
step-by-step procedures to perform the required PHY-01 through
PHY-04 and TSG-01 through TSG-12 (except TSG-07 and TSG-08,
which are optional for all components) tests of the Serial ATA
Interoperability Program using the BERTScope by SyntheSys
Research, Inc., in order to qualify a device for listing on
the SATA Integrators List.
• The test setup is illustrated in Appendix B.
• The tests may be performed in the sequence shown
in Appendix E or automated using software. Contact SyntheSys Research for the availability of such software.
Download PDF - 2 MB |
|
Poster: The Anatomy of Clock Recovery, Part 2
• Guy Foster • MAR 2006
Abstract +
- Our colorful, informative posters introduce
basic principles and applications of foundational techniques
in signal integrity testing. They are about testing digital high
speed communications electronics, and are intended for electronics
engineers who need to verify compliance of their products. The poster is
approximately 27” x 38” (68.5 x 96.5 cm), printed in full color on
glossy, heavyweight paper.
“Clock recovery is a common part of many measurements,
whether as part of the test setup of part of the device
under test. We're going to look at clock recovery from a practical point of view,
with emphasis on how it affects measurements… ” (SR-TN055b)
See related white paper below
Request posters |
|
Poster: The Anatomy of Clock Recovery, Part 1
• Guy Foster • FEB 2006
Abstract +
- Our colorful, informative posters introduce
basic principles and applications of foundational techniques
in signal integrity testing. They are about testing digital high
speed communications electronics, and are intended for electronics
engineers who need to verify compliance of their products. The poster is approximately
27” x 38” (68.5 x 96.5 cm), printed in full color on glossy, heavyweight
paper.
“Clock recovery
is a common part of many measurements, whether as part of the test setup of part of
the device under test. We're going to look at clock recovery from a practical point
of view, with emphasis on how it affects measurements… ” (SR-TN055a)
(See related white paper below)
Request posters |
|
The Anatomy of Clock Recovery, Part 2 • MAR 2006
Abstract +
- Clock recovery is a common part of many measurements, whether
as part of the test setup or part of the device under test. We're going to look
at clock recovery from a practical point of view, with emphasis on how it
affects measurements. This document closely mirrors the poster "The
Anatomy of Clock Recovery, Part 2" and picks up where the paper "Clock
Recovery Primer, Part 1" left off. (SR-TN059)
See related poster above
Download PDF - 1.4 MB |
|
The Anatomy of Clock Recovery, Part 1 • MAR 2006
Abstract +
- Clock recovery is a common part of many measurements,
whether as part of the test setup or part of the device under test. We're going
to look at clock recovery from a practical point of view, with emphasis on how
it affects measurements. This document closely mirrors the poster "The
Anatomy of Clock Recovery, Part 1." (SR-TN058)
See related poster below
Download PDF - 1.0 MB |
|
Measurement Brief: Exploring Power Supply Voltage
Sensitivity in an IC • MAR 2006
Abstract +
- This short paper examines the signal integrity performance
of an IC under the condition of lowered power supply voltage. It forms a
classic example of why eye diagrams cannot be relied upon as the sole
measure of system performance. (SR-TN057)
Download PDF - 0.2 MB |
|
Measurement Brief: Signal Integrity of Reference
Clock Bleed-Through in an IC • MAR 2006
Abstract +
- This paper examines some signal integrity examples related
to AMB testing, but also with wider applicability. Clock bleed-through is
examined, as well as the effect of lowered supply voltage on error performance.
The latter is a classic example of why eye diagrams cannot be relied upon as
the sole measure of system performance. (SR-TN056)
Download PDF - 0.3 MB |
|
Measurement Note: Using the XFI 'EQ Filter' to Equalize
a Channel to Enable Eye Measurements • FEB 2006
Abstract +
- The XFI 10 Gb/s electrical interface document describes eye
measurement methods using a channel equalizing filter. This note gives a brief
introduction to the topic, and shows measurements made on a suitable equalizing
filter. (SR-TN052)
Download PDF - 0.5 MB |
|
Stressed Eye: "Know what you're really testing
with" • JAN 2006
Abstract +
- There are considerable differences between the way that 10
Gb/s Ethernet (10 GbE) and 4x Fibre Channel (4x FC) go about defining timing and
amplitude settings for receiver jitter tolerance testing. These differences can
be subtle, but can have an enormous impact on the test signal, and therefore on
the success of the testing. The points raised here are equally applicable to
other stressed eyes, both optical and electrical. (SR-TN051)
Download PDF - 1.3 MB |
|
Constructing a 10 GbE Optical
Stressed Eye • JAN 2006
Abstract +
- Following on from the Stressed Eye Primer, this paper looks
at the practical construction of optical stressed eyes for 10 Gigabit Ethernet.
It also examines the standard in more detail. It is a companion to a similar
paper examining the 4x Fibre Channel standard. (SR-TN049)
See also Stressed Eye Primer paper below
Download PDF - 1.7 MB |
|
Constructing a 4x FC Optical Stressed Eye • JAN 2006
Abstract +
- Following on from the Stressed Eye Primer, this paper looks
at the practical construction of 4x Fibre Channel stressed eye. It also examines
the relevant standards in more detail. This is a companion document to one
describing the construction of a 10 Gb/s Ethernet stressed eye. (SR-TN050)
See also Stressed Eye Primer paper below
Download PDF - 1.7 MB |
2005
|
Dual-Dirac, Scope Histograms, and BERTScan Measurements • SEPT 2005
Abstract +
- Much has been written about the strengths and weaknesses of
dual-Dirac as a model for jitter measurement. The aim of this note is to give
a gentle introduction to the topic, and how the dual-Dirac relates to practical
measurements that can be made with sampling scopes and BER-based instruments.
(SR-TN045)
Download PDF - 1.1 MB |
|
Evaluating Stress Components Using BER-Based Jitter
Measurements • SEPT 2005
Abstract +
- Stressed eye testing allows the introduction of different kinds of
jitter components. How can the user tell whether the right amount is being
introduced? What will different components look like when measured with deep
BER-based jitter analysis? This paper examines these questions using the BERTScope
S 12500A as the basis. (SR-TN046>
Download PDF - 1.1 MB |
|
Stressed Eye Primer v. 1.1 • SEPT 2005
Abstract +
- Many high-speed serial interface standards call for a test known
as 'Stressed Eye.' This paper is an introduction to stressed eye testing, some
of the high-speed standards that use it, and how a receiver test using stressed
eye is constructed. (SR-TN038)
See also papers about constructing optical
stressed eyes, above
Download PDF - 1.1 MB |
|
Measurement Brief: Comparing Sampling Scope and
BERTScope Jitter Measurements • JULY 2005
Abstract +
- Eye diagrams are constructed fro voltage samples
taken at a rate many times lower than the data rate. The traditional method of
measuring jitter on an eye diagram is to place a window around the eye diagram
crossing point, and the build a histogram of the samples that were taken in that
region alone. From the shape and width of the histogram, an estimate of jitter is
made.
There are a number of disadvantages of this approach. The biggest
one is depth, or the fact that the source of data shows so little of what is really
going on. Most sampling scopes take data at the rate of a hundred kilo-samples per
second. The best (including the BERTScope eye diagram) are in the mega-samples per
second range. (SR-TN043)
Download PDF - 0.4 MB |
|
Measurements of Pre-Emphasis on Altera®
Stratix®GX with the
BERTScope 12500A • JUNE 2005
Abstract +
- This paper gives a brief overview of signal integrity measurements
made with the Stratix GX device from Altera. It gives quantifiable measurement of
the effectiveness of the pre-emphasis function that is available on the Stratix GX
family. It employs Eye Diagram, Jitter and BER Contour functions of the BSA 12500A
to reveal the part's performance. (SR-TN040)
Download PDF - 1.0 MB |
|
Compliance Contour — Bridging the Gap between
BER and Mask Testing for XFI, PCI-Express,
OIF-CEI • JUNE 2005
Abstract +
- It's an age old problem - systems are expected to operate to
better than 1x10^-12, but measurement to such levels takes too long. A straight
BER measurement also doesn't indicate the margin available in the design. A
solution to the speed problem has been to characterize a transmitter in terms of
an eye diagram mask test, which is fast and lends itself to sampling scope-style
measurement. Mask tests are usually shallow - an assessment of device performance
will be made on a few hundred or thousand samples. The challenge is to use these
shallow measurements to assess whether a device will exhibit problems that may be
one in a billion. This is often achieved by extrapolation or de-rating - making
the size of the mask sufficiently large or difficult, that a device that passes it
must also be operating satisfactorily down to 1x10^-12. There are several problems
with this, including the obvious risks of an extrapolation of nine orders or
magnitude in any situation; there is also the danger that too stringent a de-rating
has been specified in order to catch corner case problems, and consequently good
devices are being failed needlessly. (SR-TN041)
Download PDF - 0.2 MB |
|
The Importance of Delay Line Accuracy in Making Direct BERTScan
Measurements • JUNE 2005
Abstract +
- Many standards use the BERTScan, or BER Bathtub, as the compliant
method for measuring jitter. These include MJSQ, Fibre Channel, Gigabit Ethernet and
many others. Some standards specify that the operating jitter performance must be
measured down to a BER of 1x10^-12. Others allow some degree of extrapolation from
measurements made at higher equivalent BERs, acknowledging that the accuracy will be
lower. This paper will give some practical ways of quantifying the suitability of an
individual instrument for making accurate and repeatable direct measurements to a
specified BER level. (SR-TN039)
Download PDF - 0.2 MB |
|
BERTScope-Based Signal Integrity Compliance Testing
• Tom Waschura • JAN 2005
Abstract +
- Signal integrity compliance testing varies
from application to application, but recurring themes are emerging to help
multi-gigabit systems designers assure interoperability. Most of the tests
needed to qualify a part or system can be performed with bit error rate testers
and oscilloscopes; however a new generation of instrument, a BERTScope, takes
advantage of naturally deep measuring capability, an integrated pattern
generator (with calibrated stress), tightly-coupled eye diagramming, and bit
error rate measuring functions to provide complete compliance testing.
This paper describes the measurements necessary for compliance
testing as well as the features and benefits of the BERTScope for this application.
Measurements of transmitter jitter, channel performance and receiver tolerance are
described. (SR-TN037)
Download PDF - 0.5 MB
View Design Con TecPreview online |
2004
|
Selecting the Right Bit Error Rate Tester (BERT) • OCT 2004
Abstract +
- For any digital communications link, the ultimate measure of its
physical layer performance is whether the bits sent are received correctly. Bit
Error Rate (or Ratio, as it is more correctly called) measures this performance,
and BERTs are a common feature in many test labs either as BER measuring devices,
or as test pattern sources for other measurements. (SR-TN034)
Download PDF - 90 kB |
|
Anatomy of an Eye Diagram —
A Primer • OCT 2004
Abstract +
- This paper describes what an eye diagram is, how it is constructed
and common methods of triggering used to generate one. It then describes different
ways that information from an eye diagram can be sliced to gain more insight. It
also discusses some basic ways that transmitters, channels and receivers are tested.
It is designed to give an engineer new to this field a basic grasp of the concepts
commonly used. (SR-TN033)
See related poster below
Download PDF - 0.5 MB |
|
Poster: Anatomy of an Eye Diagram
• Guy Foster • OCT 2004
Abstract +
- Our colorful, informative posters introduce
basic principles and applications of foundational techniques
in signal integrity testing. They are about testing digital high
speed communications electronics, and are intended for electronics
engineers who need to verify compliance of their products. The poster is
approximately 27” x 38” (68.5 x 96.5 cm), printed in full color
on glossy, heavyweight paper.
Eye diagrams are a very successful way of quickly
and intuitively addressing the quality of a digital signal.
A properly constructed eye … often shows weaknesses in system
design… (SR-TN035)
See related white paper above
Request posters |
|
A new signal integrity test and measurement architecture for serial 10 Gb/s
interfaces • Tom Lindsay • OCT 2004
Abstract +
- New high-speed serial communications specifications such
as 10G Ethernet and OIF’s CEI create challenging demands for signal
integrity test and analysis. A novel dual-sampler Bit Error Rate test
(BERT) architecture addresses these needs by integrating eye diagram, eye
mask, jitter, Q-factor, BER, and other physical layer measurements into a
single instrument. This paper shows actual results of how these physical
layer tests can be done with far greater speed and statistical accuracy and
confidence than previously possible. (SR-TN036)
Download PDF - 1.8 MB |
|
Bridging the Gap between BER and Eye Diagrams —
A BER Contour Tutorial • OCT 2004
Abstract +
- This paper provides an introduction to the BER
Contour measurement - what it is, how it is constructed, and why it is a
valuable way of viewing parametric performance at gigabit speeds. It also
provides illustrative examples of BER Contour in action, taken with a
SyntheSys Research BERTScope 12500A 12.5 Gb/s Signal Integrity Analyzer.
(SR-TN032)
Download PDF - 0.9 MB |
|
High-Speed Digital Test of XFP MSA
Modules • article published in LIGHTWAVE •
Charlie Schaffer • MAR 2004
Abstract +
- The XFP/XFI Transceiver MSA (multi-source agreement) has developed
significant momentum in the telecommunications and datacommunications industry.
Many transceiver manufacturers, including Bookham, JDSU, Agilent Technologies,
Finisar, MergeOptics, Intel, Infineon, Opnext, Picolight, and Sumitomo Electric,
have announced XFP modules and a number of communications IC vendors having announced
devices in support of the standard. Perhaps most important, at least one key
equipment manufacturer, Cisco, has committed to the new interface. Unlike the other
10 Gb MSAs, the XFP transceivers feature a 10 Gb/s differential I/O
interface—XFI “ziffy”— instead of a 16-channel SERDES
found in the 300-pin MSA and 4-channel Xaui in Xenpacks, Xpaks, and X2. Though the
other MSAs will doubtless continue to be used for some time, many in the industry
expect XFP to become the dominant 10 Gb optical interface for applications other
than DWDM and long haul transport. (SR-TN031)
Download PDF - 0.5 MB
Article reproduction (not printable) - 120 kB
Read article at LIGHTWAVE |
2003
|
Using Bit Error Rate Testers to Drive Forward Error Correction Codes
• Tom Waschura • SEPT 2003
Abstract +
- Forward Error Correction is a critical component in many modern
digital communications applications, turning otherwise unusable communications
links into real and practical systems. From DVDs to cell phones,
satellite TV to disk drives, error correction technology is a mathematical marvel
that effectively makes a silk purse from a sow’s ear. (SR-TN029)
Download PDF - 0.4 MB |
|
Innovations in BER testers enable fast and accurate eye diagram, eye mask,
Q-factor, and jitter measurements
• Tom Lindsay • SEPT 2003
Abstract +
- Successful integration of fast and accurate eye diagram, eye mask,
jitter, and Q-factor functions into a BERT has been demonstrated. These measurements
can be done with far greater speed and statistical accuracy than previously possible.
• ©2003 Optical Society of America • OCTS codes:(120.4800) Optical
standards and testing; (060.2330) Fiber optics communications (SR-TN030)
Download PDF - 0.4 MB |
2002
|
BER Testing for SFI-4 Applications •
Jim Dunford • MAY 2002
Abstract +
- Manufacturers and integrators of optical networking modules
have worked together to specify mechanical and electrical interfaces in order
to promote module-to-module interoperability. One such agreement is the SFI-4
standard for the OC-192 framer-to-SERDES interface developed by the Optical
Internetworking Forum. This white paper provides background on the SFI-4 interface
and presents a means for characterization of Bit Error Rate performance of
transceiver systems at the SFI-4, and other similar interfaces. (SR-TN014)
Download PDF - 0.3 MB |
2001
|
Testing Applications in Uncompressed HDTV
Signals • Jim Waschura • NOV 2001
Abstract +
- This paper focuses on testing methods and applications for the
uncompressed HDTV signal, SMPTE 292M. It includes a description of the signal's
electrical characteristics, digital format, and special protocols for embedding
auxiliary information. This is followed by an explanation of testing methodologies
and tools used to verify compliance to the SMPTE specification. Afterwards, the
author suggests two specific areas for automatic testing in the product
manufacturing cycle: design verification and manufacturing test. (SR-TN023)
Download PDF - 0.5 MB |
|
SDI Testing — A Toolbox at Your Fingertips
• Jim Waschura • NOV 2001
Abstract +
- Yes, we've all heard it: "Digital is perfect;
why would I want to test it?" And largely, this sentiment reflects the reality
of many off-line or noncritical video system installations.
At installations that are time-critical, however, like live production
and broadcasting, engineers know that being able to quickly diagnose a problem can
help them to make repairs rapidly and save on equipment and personnel downtime.
In addition, engineers involved in system installation and maintenance
are aware that compatibility between system components and signal quality are the two
most important indicators of system robustness.
Of course, the developers of video systems know that evaluating
quality of their systems before shipping translates to a higher "out of the
box" success rate, which means more customer satisfaction and repeat business.
(SR-TN022)
Download PDF - 0.3 MB |
|
Bit Error Location Analysis for Instrumentation Recording Applications
• NOV 2001
Abstract +
- This paper describes techniques for error location analysis
used in the design and testing of high-speed instrumentation data recording and
communications applications. It focuses on the differences between common bit
error rate testing and new error location analysis. Examples of techniques
presented include separating bit and burst error components, studying probability
of burst occurrences, looking at error free interval occurrence rates as well as
auto-correlating error position. Each technique contributes to a better
understanding of the underlying error phenomenon and enables higher-quality
digital recording and communication. Specific applications in error correction
coding emulation, magnetic media error mapping, and systematic error interference
are discussed. (SR-TN024)
Download PDF - 0.2 MB |
|
Application Note: Error Correction Coding
Emulation • SEPT 2001
Abstract +
- ID1-type tape recorders are widely used in
industry today. This type of recorder uses eight helical scanning heads to
sequentially read data off magnetic tape. Each head reads a track length of
36,108 user-data bytes (288,864 bits) recorded on the tape at a 5-degree angle.
When data is recorded to an ID1-type tape, it is interleaved
according to the ID1 standard. Likewise, data scanned from these tapes is passed
through three-dimensional Reed-Solomon Error Correction Coding, which corrects
and de-interleaves the data back into user format.
In analysis of ID1 error data, it is most useful to re-interleave
the output data back into the tape format for error measurement and analysis purposes.
This is easily accomplished through the use of the BitAlyzer ECC option.
The paper describes hardware interfacing, ID1
interleaving, ID1 de-interleaving, and BitAlyzer re-interleaving. Several analysis
examples are included as well. (SR-TN027)
Download PDF - 0.4 MB |
2000
|
Error Location Analysis Tutorial • MAY 2000
Abstract +
- Bit error rate testing has always been a useful
development tool. In most cases, however, a simple bit error rate does
little—if anything—to identify the sources of errors. For that, you
need error location analysis.
The patented error location analysis methods used in SyntheSys Research's
BERTScopes and BitAlyzers offer you the opportunity to study your bit errors in detail,
helping you find relationships that uncover the cause behind errors. Here is how to learn
more about what error location analysis is and how different types of analysis can be used
under various conditions.
View online |
|
Bit Error Analysis and Beyond • MAR 2000
Abstract +
- In the past, bit error rate testing meant transmitting a
pseudo-random sequence of bits through a channel under test and counting the
number of incorrectly received bits at the receiving end. This technique was
adequate because the basic question to be answered was, "is it working?"
Today's communication systems are pushing the envelope further and further,
trying to squeeze as much bandwidth out of a channel as possible, and the question
has now become, "How can I make it work better?" Forward error correction,
data compression, and sophisticated modulation codes are some examples of these
techniques. In these systems, knowing the position of an error relative to the data
being transmitted or relative to other errors, is crucial in order to optimize the
efficiency of a given technique. This class discusses many techniques for bit-accurate
analysis, and discusses the concept of an overall system error budget.
(SR-TN015)
Download PDF - 0.3 MB |
1998
|
Digital Channel Error Correction
Coding Design Tools • 1998
Abstract +
- Error correction coding theory describes
ways to add overhead to transmitted or stored messages to
insure that they can be understood when received or played
back. Challenging implementations of error correction
coding theory are responsible for many advances in
digital communications applications ranging from deep
space exploration to high-density disk drives, cellular
telephones and pager networks. (SR-TN012)
Download PDF - 0.2 MB |
|
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