Interpreting a Pattern Sensitivity Analysis

Pattern Sensitivity happens when one part of the test data sequence results in more bit errors than another part. This is also called data-dependent errors. Pattern sensitivity happens for a variety of reasons and can be isolated by looking at the Pattern Sensitivity analysis built in to the BERTScope/BitAlyzer.

For a particular pseudo-random bit sequence (PRBS) pattern, this analysis tries to correlate errors with particular sequences in the received signal. This is a variation of Correlation Analysis, where the instrument automatically sets the correct number of correlation bins for the pattern being transmitted. It is also able to compute the exact data value at each bit position, and therefore overlay the exact bit sequence onto the correlation graph. This gives you the ability to isolate exact pattern sequence errors.

The cursor-highlighted "1" bit in this example shows a case where a number of times this bit came in as a zero. These errored zero bits are analyzed in the Pattern Sensitivity analysis and accumulated in the exact bit position corresponding to the data bit that caused the error.

Examples

	1a. This graph shows pattern sensitivity — that is, the peak underneath the cursor shows which bit is coming in incorrectly as well as the number of times it came in wrong. The sequence preceding this may be problematic and causing the error.
	1b. This graph shows an example with no pattern sensitivity evident. Errors are distributed randomly with respect to the transmitted PRBS sequence being used so all bit positions have the same probability of error. Even in this case, the cursor is active and you can examine the data pattern used.

	2a. This graph shows pattern sensitivity to a long sequence of zeros, followed by an isolated one — the one is often errored.
	2b. An example of what might cause this could be a device under test that has trouble making the isolated one reach full height, and it is therefore sometimes appearing as a one, and sometimes a zero.

Examples of Problematic Patterns

1. Long runs of ones or zeros are a problem for clock recovery circuits. The lack of transitions could make the circuit lose lock, or increase jitter on the recovered clock signal. Transitions between many ones to many zeros may cause ground bounce on internal integrated circuits or ECL termination current starvation.

2. A clock recovery circuit might find this pattern difficult, as the PLL may beat with the lower square wave frequency and fail to find lock.

3. This pattern may produce a bandwidth-limiting problem. The natural system is trying to round out the zero and force it to be a one to continue the pattern. This is typical LPF behavior.

4. Isolated one could be high frequency bandwidth limit, notching, GaAs lazy shoulder from capacitive charging.

5. Hard to turn on device after being fully turned off — possibly a laser biasing problem.

6. This type of pattern can often cause errors in magnetic recording. Magnetic dipoles attract each other and shift bit cell edges together.