Pass PCI Express Physical Layer Compliance Testing the First Time

On-Demand Webcast  †

Speaker: Bent Hessen-Schmidt, Vice President, Business Development, SyntheSys Research, Inc.

Moderator: Rick Nelson, Editor in Chief, Test & Measurement World

Hosted by Test & Measurement World and EDN • DEC 2007
ON-DEMAND WEBCAST – Registration required.

With the PCIe 2.0 specification, 5.0 GT/s and 2.5 GT/s receiver testing are emerging as key requirements for chip designers and add-in card vendors. In this seminar we look at why the requirements have been set the way they have, and some of the practicalities of making the measurements. We will then look at key transmitter measurements such as PLL characterization, jitter measurement in the presence of de-emphasis, de-emphasis ratio, and dual port measurements. Measured examples of real devices will be used to illustrate the requirements.

• Learn why some key aspects of the standard are the way they are, including system architecture and the importance of clock distribution.
• Understand the important aspects of transmitter, clock PLL and receiver testing.
• See practical example measurements of each.

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