Come see BERTScope at DesignCon 2007— We will feature 5 new tools   to meet the challenges of PCIe Gen2, SATA, and 802.3 jitter analysis.  SyntheSys Research engineers will present solutions to some of the toughest challenges in today’s signal integrity margin and compliance testing:

• Equalize transmitter and backplane measured signals to show real ‘eye opening’ for 802.3ap;
• Accurately capture SSC waveforms for SATA and generate adjustable center-spread SSC for SAS Gen3;
• Analyze duty cycle distortion of sub-rate clocked systems;
• Measure 1.5 MHz low pass filter integrated jitter spectrum for PCIe Gen2;
• Generate differential pre-emphasis signals from a single-channel BERT.

Contact us at sales@bertscope.com to schedule a private product demo and get ahead of your competition!  Or visit us at the SyntheSys Research Booth #619.  We'll also be presenting at the BERTScope TecPreview Session on Tuesday, January 30, from 4:30pm to 4:50pm in the TecPreview Theater.

"Clock recovery's impact on test and measurement"
Guy Foster
LIGHTWAVE Magazine, November 2006

Clock recovery plays a significant role in making accurate test measurements, whether incorporated into the test setup or as part of the device under test.  As most gigabit communication systems are synchronous, the data within them are timed against a common clock.  Whether traveling across inches of circuit board or traversing continents on optical fiber, the relationship between the data and the clock they were timed against can become disturbed.  By extracting clock directly from the data, signal regeneration at the receiver can be achieved correctly.   ››For the full story…

PCI Express 1.0a and 1.1 Add-In Card Transmitter Testing
Joan Gibson
November 2006

Add-in cards designed for PCI Express require numerous tests to assure inter-operability with different systems.  This document describes testing to verify transmitter compliance with the PCI Express Card Electromechanical Specifications Revision 1.0a and Revision 1.1, and highlights three important areas in compliance testing:

• Accurate views for de-emphasis measurements
• Edge density requirements for clock recovery
• The speed of making mask tests

For the full story…

Serial ATA Interoperability Program Method of Implementation (MOI)
Revision 1.1 Version 1.0 for PHY and TSG Device Certification Tests using the BERTScope by SyntheSys Research, Inc.
December 2006

These Methods of Implementation describe the step-by-step procedures to perform the required PHY-01 through PHY-04 and TSG-01 through TSG-12 (except TSG-07 and TSG-08, which are optional for all components) tests of the Serial ATA Interoperability Program, using the BERTScope by SyntheSys Research, Inc., in order to qualify a device for listing on the SATA Integrators List.

For the full story…

Question: How do I get my PCIe product into loopback mode for receiver tolerance testing?

Answer: Well, the BERTScope has the capability to transmit the appropriate TS1 and TS2 training sequences to initiate loopback followed by your desirable test pattern. If your product is a multi-lane device, then you must first either modify the Compliance Base Board or use a single lane adapter; our solutions engineers will be happy to tell you how. Did you know that the BERTScope can also automatically step the jitter frequency and amount to search for the maximum jitter that your receiver can tolerate?

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Stop by Booth #619

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