BERTScope Newsletter  February 2009
 
Welcome

Welcome to the BERTScope Newsletter – the latest hints, tricks, and tutorials on signal integrity measurements from SyntheSys Research, Inc. We hope that you will enjoy this and future editions.


How-to Articles

Testing an SFP+ Transceiver to the 8x Fibre Channel Specifications, Part I

Product Note: Testing an SFP+ Transceiver to the 10 Gigabit Ethernet Electrical Specifications
The paper examines the electrical input and output specifications of a limiting variant SFP+ transceiver and active SFP+ cable for 10GbE applications, and provides a practical example demonstrating compliance testing.

PCI Express 5.0 GT/s Add-In Card Receiver CEM Testing

PCI Express® 5.0 GT/s Add-In Card Receiver CEM Testing This paper describes testing to verify receiver compliance with the PCI Express Card Electro-Mechanical (CEM) Specification Revision 2.0.

Measuring PLL Loop Bandwidth Using a BERTScope

Measuring PLL Loop Bandwidth Using a BERTScope Understanding phase lock loop (PLL) response is important for the design and verification of digital communication networks. This paper shows PLL measurement examples, each made using the BERTScope with automation software.

Great Resources

Jitter Mapping Tools

Upcoming BERTScope EDN eSeminar: Why different instruments give different
jitter answers"

February 26, 10:00AM PST / 1:00PM EST
Register here.

What's New at SyntheSys?

BERTScope Si 17.5 Gb/s Analyzer

BERTScopes now go faster – 17.5 Gb/s BERTScope Si 17500C ...Read More

Jitter Map: BER-based jitter decomposition BER-based jitter decomposition – Jitter Map can help you, even with PRBS-31 challenges ...Read More
DisplayPort

BERTScope is the only approved solution for DisplayPort™ CTS 1.1 sink testing. See our solution here.

DesignVision Award Winner 2009

We were pleased to be named a DesignVision Award Winner for 2009 for the BERTScope DPP 4-tap pre-emphasis instrument. Read about the product here.

DPP Digital Pre-Emphasis Processor Interface
EDN Innovation Awards: Vote!
FINALIST

We are honored to have also been nominated for an EDN Innovation Award for the DPP. We would appreciate it if you would vote for us in the "Instruments" category (voting is open until Friday, February 27) here.

Come and See Us at...

PCI-SIG Compliance Workshop
Milpitas, California February 23-27, 2009

PCIe® DevCon Europe
Frankfurt, Germany March 9-10, 2009

OFC 2009
San Diego, California March 22-26, 2009


Question: Is random jitter (RJ) the same on every bit of the pattern?

Answer: MJSQ[1] defines the mathematical quantity RJ, as used in the dual-Dirac jitter model, as being pattern independent. In reality, the random jitter will frequently vary from bit to bit. An example might help here: Channel bandwidth effects cause different bits in a pattern of data to have different rise times or slopes. Amplitude noise on the signal move the edge by different amounts for different slopes.

The new Jitter Map option for the BERTScope family provides the RJRMS needed for MJSQ compliant measurements, but also has an RJ/bit view giving insight into pattern-related RJ. An example is here.

[1] 'Fibre Channel – Methodologies for Jitter and Signal Quality Specification' – MJSQ, T11.2, Project 1316-DT, Rev 14, June 9, 2004.


Science Puzzler

Why is it so quiet just after a snowfall? There may not be as many people or cars outside as usual, but that alone doesn’t explain such quietness. Where does the energy of the outside noise go? Why does the snow have to be fresh?

(Click for Answer)

 

Quote of Note

The early bird may get the worm, but the second mouse gets the cheese.

— Anonymous

Guess What?

Guess What?

(Click for answer)


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© 2009 SyntheSys Research, Inc. All Rights Reserved.

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