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How-to Articles
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Why Do Different Instruments
Give Different Jitter Answers? Application Note
Signal integrity engineers complain that every high speed
instrument in their lab gives a different answer when measuring
jitter. Here we look at some reasons why ...
Read More
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Getting the Right Stress at the IC Pins –
De-Embedding with BERTScope
The product note discusses a methodology for delivering
an accurate, calibrated stressed eye to the pins of an IC under test; as an example,
using compensation of a 17-inch trace to deliver a compliant SFP+ stressed eye
... Read More
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Testing an SFP+ Transceiver to the
10 Gigabit Ethernet Electrical Specs
In this product note, we examine the transmitter electrical input specifications and
receiver electrical output specifications of a limiting variant SFP+ transceiver and
active SFP+ cable for 10 Gigabit Ethernet (10GbE) applications ... Read More |
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Great Resources
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Jitter Map "Under the Hood" – A New Methodology for
Jitter Separation
Jitter Map, an innovative new capability on the BERTScope, bridges the gap between
sophisticated jitter component analysis using oscilloscopes and the confidence of
deep, BER-based total jitter measurements ... Find out more here
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What's New at SyntheSys?
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BER-based jitter decomposition – Jitter Map can
help you, even with PRBS-31 challenges ... Read more about our introductory offers |
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BERTScopes now go faster – Check out the new
BERTScope Si 17500C
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BERTScope is the only approved solution for DisplayPort™
CTS 1.1 sink testing. See our DisplayPort solution here. |
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Come and See Us at... |
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PCI-SIG APAC Compliance Workshop #66
Taipei, Taiwan April 20-24, 2009 |
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SATA-IO Interop #7 / SATA-IO Plugfest #12
Milpitas, California June 8-11, 2009 |
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PCI-SIG Developers Conference 2009
Santa Clara, California July 15-16, 2009 |
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