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Clock Recovery CR/CR HS 12.5/14.3/26/28 Gb/s
CRJ 12500A & Option 143
CR with Jitter Analysis
DCRJ Digital Communications
Receiver with Jitter Analysis
PLA Clock PLL Response Analyzer
Clock Recovery Feature Selection Guide


 

 

BERTScope PLA
BERTScope PLA Phase Lock Loop Analyzer
RELATED MATERIAL
Download PDF PLA PLL-PCIe Product Brief PDF
Download PDF PCIe Transmitter PLL Testing - A Comparison of Methods PDF
Download PDF PCI Express MOI (Rev1.1) Test Methodology for PLL Loop Bandwidth Response in Add-in Cards - Testing Guide PDF
Download PDF PCI Express MOI (Rev2.0) Test Methodology for PLL Loop Bandwidth Response in Add-in Cards - Testing Guide PDF
Design Vision Award Finalist 2008
A Complete PLL Compliance Test Solution
for PCIe Components and Add-In Cards

  • Simple Compliance Test
  • Accurate
  • Repeatable
  • Single Instrument Solution

The BERTScope PLA is an easy to use, single instrument measurement solution for PLL loop response characterization and compliance testing to the PCIe specifications. The instrument features fast setup as well as accurate and repeatable results.

Ease of Use
Of all the methods for testing PLL compliance in PCIe components and add-in cards, the BERTScope PLA analysis instruments are the easiest to set up and use. Simply connect four cables to the Compliance Base Board, plug the instrument’s USB cable into any PC, load the software, and you are up and testing. No specialized instrument setups or calibration runs are required.

Pass-Fail determination is just as easy. The simplified user interface allows any user to quickly get the compliance test results they need, without complicated cursor setup or interpretation that is required using other methods.

BERTScope PLA : PLL-PCIe screenshot Works with All PCIe PLL Topologies
The BERTScope PLA reference generator maintains a duty cycle of exactly 50%, regardless of the amount of frequency modulation, allowing the instrument to test any PLL topology. Other instruments amplitude-modulate the 100 MHz reference oscillator, essentially modulating the duty cycle rather than the period. While this technique works with single-edge phase detectors, it won’t work with PLLs using dual-edge detectors that new designs incorporate to reduce the multiplier ratio, resulting in lower clock jitter.

Fast
The instrument sweeps the full range of test frequency in under 15 seconds. Unlike spectrum analyzers, which must reduce the sweep time to achieve good frequency resolution, the BERTScope PLA analysis instrument always maintains full resolution without slowing down test time. The fast measurements improve design confidence, allowing the characterization of a large number of devices without adding extra days of characterization to a design introduction schedule.

Highly Accurate and Repeatable
The BERTScope PLA does not sacrifice accuracy and resolution to achieve ease of use and fast test times. An amplitude measurement resolution of 0.01 dB provides high confidence when testing the peaking limit to the +1 dB allowed by the standard. Other approaches have limited resolution of 0.5 or even 1 dB, limiting the ability to accurately measure peaking and -3 dB bandwidth.

The high measurement resolution and clean reference oscillator provide the granularity required for consistent results – validated through dozens of tests at compliance workshops. Other methods with limited resolution can give less decisive results. Test made today with the BERTScope PLA will agree with those made last week, or in another lab using a different BERTScope PLA.

More than Just Compliance Testing
The BERTScope PLA provides additional measurements useful for the PLL designer to characterize their design In addition to directly measuring the edge density of the Tx data, the BERTScope PLA can also generate a phase plot, allowing the designer to see the phase margin of the PLL.

The instrument provides both high resolution and high dynamic range — typically 75 dB. This allows the user to see the transfer of low frequency jitter sources, orders of magnitude below the PLL – 3 dB point. The SSC modulation jitter component can be directly measured.

The CRJ 12500A-PCIe combines the powerful spectral jitter analysis and instrumentation quality clock recovery functionality of the CRJ 12500A with PCIe-PLL analysis. All of the CRJ 12500A features and specifications are maintained in the CRJ 12500A-PCIe model.

Clock Recovery Selection Guide

Maximum Data Rate, Gb/s Models Jitter Spectrum to
12.5 GHz
Optional PLL Analysis (Option PCIE) Loop Bandwidths, Maximum Rate of Operation Data Through-Path
Standard 12 MHz 24 MHz Extension (Option XLBW) Internal Pick-Off Tee High Sensitivity, Direct Input
12.5  CR 12500A 12.5 Gb/s 12.5 Gb/s
 CRJ 12500A
 CRJ 125-PCIE
14.3  CRJ 12500A
   Option 143
14.3 Gb/s *
 CR 14300A
26  CR 25000A 26 Gb/s
 CR HS 25000A
28.6  CR 28000A 28.6 Gb/s *
 CR HS 28000A

*Data through-path recommended for use below 12.5 Gb/s. Above this rate, use of an external
  pick-off tee is advised.

 

Ordering Information:

Product Code Description
CRJ 125A-PCIE BERTScope CRJ Clock Recovery Instrument with Jitter and PLL Analysis

Contact your sales representative for more information.

 

PCI Express and PCIe are registered trademarks of PCI-SIG.

 

 

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